A processor needs software interrupt to
1.test the interrupt system of the processor
2.implement co-routines
3.obtain system services which need execution of privileged instructions
4.return from subroutine
A system that has a lot of crashes, data should be written to the disk using?
1.write – through
2.write – back
3.both (a) and (b)
4.None of the above
Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non pipelined but identical CPU, we can say that
1. T1 <= T2
2. T1 >= T2
3.T1 < T2
4. T1 is T2 plus the time taken for one instruction fetch cycle
In 2' s complement addition, overflow
1.is flagged whenever there is carry from sign bit addition
2.cannot occur when a positive value is added to a negative value
3.is flagged when the carries from sign bit and previous bit match
4.None of the above
Suppose a processor does not have any stack pointer register. Which of the following statements is true?
1.It cannot have subroutine call instruction
2.It can have subroutine call instruction, but no nested subroutine calls
3.Nested subroutine calls are possible, but interrupts are not
4.All sequences of subroutine calls and also interrupts are possible
The 2’s complement representation of (−539)10 in hexadecimal is
1.ABE
2.DBC
3.DE5
4.9E7
The Principle of locality justifies the use of
1.Interrupts
2.Threads
3.DMA
4.Cache memory
A 32-bit address bus allows access to a memory of capability
1.64 GB
2.16 GB
3.1 GB
4.4 GB
A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be
1.120.4 microseconds
2.160.5 microseconds
3. 165.5 microseconds
4. 590.0 microseconds
A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non-privileged
1.a hardware interrupt is needed
2.a software interrupt is needed
3.a privileged instruction (which does not generate an interrupt) is needed
4.a non-privileged instruction (which does not generate an interrupt is needed
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while
1.INTA is active
2.HOLD is active
3.READY is active
4.None of These
A hardware interrupt is
1.Also called an internal interrupt
2.Also called an external interrupt
3.An I/O interrupt
4.A clock interrupt
A low memory can be connected to 8085 by using
1.INTER
2.RESET IN
3.HOLD
4.READY
Addressing mode is …………………
1.Explicitly specified
2.Implied by the instruction
3.Both a and b
4.Neither a nor b
An instruction cycle refers to
1.Fetching an instruction
2.Clock speed
3.Fetching, decoding, and executing an instruction
4.Executing an instruction
Assuming all numbers are in 2's complement representation, which of the following numbers is divisible by 11111011?
1.11100111
2.11100100
3.11010111
4. 11011011
………… improve system performance by temporarily storing data during transfers s/w devices or processers that operate at different speeds.
1.Caches
2.Controllers
3.Buffers
4.Registers
Consider the grammar rule E → E1 - E2 for arithÂmetic expressions. The code generated is targeted to a CPU having a single user register. The subÂtraction operation requires the first operand to be in the register. If E1 and E2 do not have any comÂmon sub expression, in order to get the shortest possible code
1.E1 should be evaluated first
2.E2 should be evaluated first
3.Evaluation of E1 and E2 should necessarily be interleaved
4.Order of evaluation of E1 and E2 is of no consequence
Consider the values A = 2.0 x 10^30, B =-2.0 x 10^30, C= 1.0, and the sequence X: = A + B Y: = A + C X: = X + C Y: = Y + B executed on a computer where floating-point numbers are represented with 32 bits. The values for X and Y will be
1.X = 1.0, Y = 1.0
2.X = 1.0, Y = 0.0
3.X = 0.0, Y = 1.0
4. X = 0.0, Y = 0.0
For a pipelined CPU with a single ALU, consider the following situations 1. The j + 1-st instruction uses the result of the j-th instruction as an operand 2. The execution of a conditional jump instruction 3. The j-th and j + 1-st instructions require the ALU at the same time Which of the above can cause a hazard ?
1.1 and 2 only
2. 2 and 3 only
3.3 only
4.All of the above
Horizontal microprogramming :
1.does not require use of signal decoders
2.https://compsciedu.com/mcq-questions/Computer-Architecture/GATE-cse-question-paper/8#:~:text=results%20in%20larger%20sized%20microinstructions%20than%20vertical%20microprogramming
3.uses one bit for each control signal
4.All of the above
ID catching system, the memory reference made in any short time integral tends to use only a small fraction of the total memory?
1.Checker boarding
2.Locality principle
3.Memory interleaving
4.None of the above
If 73x (in base-x number system) is equal to 54y (in base-y number system), the possible values of x and y are
1.8,16
2.10,12
3.9.13
4.8.11
In a 16-bit instruction code format 3-bit operation code, 12-bit address, and 1 bit is assigned for address mode designation. For indirect addressing, the mode bit is
1.0
2.1
3.Pointer
4. Off - Set
In the absolute addressing mode
1.the operand is inside the instruction
2.the address of the operand is inside the instruction
3.the register containing address of the operand is specified inside the instruction
4.the location of the operand is implicit
Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2's complement numbers. Their product in 2's complement is
1.1100 0100
2.1001 1100
3.1010 0101
4.1101 0101
Microinstruction length is determined by ……………….. 1) The maximum number of simultaneous micro-operations that must be specified 2) The way in which the control information is represented or encoded 3) The way in which the next microinstruction address is specified
1.1 and 2
2.2 and 3
3.1 and 3
4.All of the above
Pipelining improves CPU performance due to?
1.Reduced memory access time
2.Increased clock speed
3.The introduction of parallelism
4.Additional functional units
Sign extension is a step in
1.floating point multiplication
2.signed 16 bit integer addition
3.arithmetic left shift
4.converting a signed integer from one size to another
Spatial locality refers to the problem that once a location is referenced
1.It will not be referenced again
2.It will be referenced again
3. A nearby location will be referenced soon
4.None of the above
System calls are usually invoked by using 1) An indirect jump 2) A software interrupt 3) Polling 4) A privileged instruction
1.2 and 3
2.1 and 3
3.1, 2, 3 & 4
4.3 & 4
The 2' s complement representation of the decimal value - 15 is
1.1111
2.11111
3.111111
4.10001
The 8085 microprocessor responds to the presence of an interrupt
1.As soon as the TRAP pin becomes 'high'
2.By checking the TRAP pin for 'high' status at the end of each instruction fetch
3.By checking the TRAP pin for 'high' status at the end of the execution of each instruction
4.By Checking the TRAP pin for 'high' status at regular intervals
The complement of the function F = (A + B’)(C’ + D)(B’ + C) is:
1.A’B + CD’ + BC'
2. AB’ + C’D + B’C
3. AB’ + CD’ + BC
4. AB + BC + CD
The most appropriate matching for the following pairs X: Indirect addressing 1 : Loops Y: Immediate addressing 2 : Pointers Z: Auto decrement addressing 3: Constants is
1.X-3, Y-2, Z-1
2.X-I, Y-3, Z-2
3.X-2, Y-3, Z-1
4. X-3, Y-l, Z-2
The performance of a pipelined processor suffers if
1.the pipeline stages have different delays
2.consecutive instructions are dependent on each other
3.the pipeline stages share hardware resources
4.All of the above
The register which holds the address of the locating to or from which data are to be transferred is known as
1.Index register
2.Instruction register
3.Memory address register
4.Memory data register
The system bus consists of
1.Data bus
2.Data bus and address bus
3.Data bus and control bus
4.Data bus, control bus and address bus
The word length of a CPU is defined as
1.The maximum addressable memory size
2.The Width of a CPU register
3.The width of the address bus
4.The number of general purpose CPU registers
To prevent signals from colliding on the bus, ……………….. Prioritize access to memory by I/o channels and processors.
1.A register
2.Interrupts
3.The processor scheduler
4.A controller
To put the 8085 microprocessor in the wait state
1.lower the-HOLD input
2.lower the READY input
3.raise the HOLD input
4.raise the READY input
What are the states of the Auxiliary Carry (AC) and Carry Flag (dCY) after executing the following 8085 program? MVI L, 5DH MVI L, 6BH MOV A, H ADD L
1.AC = 0 and CY = 0
2.AC = 1 and CY = 1
3.AC = 1 and CY = 0
4.AC = 0 and CY = 0
Which addressing mode is suitable for a high-level language statement?
1.Auto increment
2.Indexed
3.Displacement
4.Auto decrement
Which is the most appropriate match for the items in the first column with the items in the second column: X. Indirect Addressing I. Array implementation Y. Indexed Addressing II. Writing re-locatable code Z. Base Register Addressing III. Passing array as parameter
1.(X, III) (Y, I) (Z, II)
2.(X, II) (Y, III) (Z, I)
3.(X, III) (Y, II) (Z, I)
4.(X, I) (Y, III) (Z, II)
Which memory unit has the lowest access time?
1.Cache
2.Registers
3.Magnetic disk
4.Main memory
Which of the following addressing modes are suitable for program relocation at run time ?
1.Absolute addressing
2.Based addressing
3.Relative addressing
4.Indirect addressing
Which of the following holds data and processing instructions temporarily until the CPU needs it??
1.ROM
2.Control unit
3.Main memory
4.Coprocessor chips
Which of the following is not a valid class of interrupts? 1) Program 2) Timer 3) I/o 4) Hardware failure
1.1 and 3
2. 1, 2 and 4
3.2 and 3
4.None of the above
Which of the following is not involved in a memory write operation?
1.MAR
2.PC
3.MDR
4.Data bus
Which of the following register processors used for fetch and execute operations? 1) Program counter 2) Instruction register 3) Address register
1.1 and 3
2. 1 and 2
3. 2 and 3
4.1,2 and 3