When the R/W bit of the status register of the DMA controller is set to 1.

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Question:
 When the R/W bit of the status register of the DMA controller is set to 1.

1.Read operation is performed

2.Write operation is performed

3.Read & Write operation is performed

4.None of the mentioned

Posted Date:-2021-03-15 06:09:27

More MCQS Questions and answers

  1. In synchronous BUS, the devices get the timing signals from __________
  2. After the device completes its operation _____ assumes the control of the BUS.
  3. Asynchronous mode of transmission is suitable for systems with multiple peripheral devices.
  4.  If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration.
  5.  In IBM’s S360/370 systems _____ lines are used to select the I/O devices.
  6.  The asynchronous BUS mode of transmission allows for a faster mode of data transfer.
  7.  The conversion from parallel to serial data transmission and vice versa takes place inside the interface circuits.
  8.  The device which is allowed to initiate data transfers on the BUS at any time is called _____
  9.  The DMA transfer is initiated by _____
  10.  The registers of the controller are ______
  11.  The side of the interface circuits, that has the data path and the control signals to transfer data between interface and device is _____
  12.  When the R/W bit of the status register of the DMA controller is set to 1.
  13. Can a single DMA controller perform operations on two different disks simultaneously?
  14. Distributed arbitration makes use of ______
  15. How is a device selected in Distributed arbitration?
  16. In Centralised Arbitration ______ is/are is the BUS master.
  17. In Distributed arbitration, the device requesting the BUS ______
  18.  The DMA controller has _______ registers.
  19. MRDC stands for _______
  20. Once the BUS is granted to a device ___________
  21. The BUS busy line is made of ________
  22. The BUS busy line is used __________
  23. The BUS that allows I/O, memory and Processor to coexist is _______
  24. The Centralised BUS arbitration is similar to ______ interrupt circuit.
  25. The circuit used for the request line is a _________
  26. The classification of BUSes into synchronous and asynchronous is based on _______
  27. The controller is connected to the ____
  28. The controller uses _____ to help with the transfers when handling network interfaces.
  29. The delays caused in the switching of the timing signals is due to __________
  30. The device which interacts with the initiator is __________
  31. The device which starts data transfer is called __________
  32. The devices with variable speeds are usually connected using asynchronous BUS.
  33. The master indicates that the address is loaded onto the BUS, by activating _____ signal.
  34. The Master strobes the slave at the end of each clock cycle in Synchronous BUS
  35. The meter in and out lines are used for __________
  36. The MSYN signal is initiated __________
  37. The parallel mode of communication is not suitable for long devices because of ______
  38. The primary function of the BUS is __________
  39. The technique where the controller is given complete access to main memory is __________
  40. The technique whereby the DMA controller steals the access cycles of the processor to operate is called _________
  41. The time for which the data is to be on the BUS is affected by __________
  42. The transmission on the asynchronous BUS is also called _____
  43. To overcome the conflict over the possession of the BUS we use ______
  44. To resolve the clash over the access of the system BUS we use ______
  45. What is the interface circuit?
  46. When the process requests for a DMA transfer?
  47. When the processor receives the request from a device, it responds by sending _____
  48. Which is fed into the BUS first by the initiator?
  49. ___ BUS arbitration approach uses the involvement of the processor.
  50. _____ serves as an intermediary between the device and the BUSes.
  51. ____________ signal is used as an acknowledgement signal by the slave in Multiple cycle transfers.
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